1. Field of the Invention
The present invention relate to an in-plane switching (IPS) mode liquid crystal display (LCD) device, and more particularly, to an array substrate for an IPS mode LCD device that can obtain a high aperture ratio and a high brightness.
2. Discussion of the Related Art
The conventional LCD devices use an optical anisotropic property and polarization properties of liquid crystal molecules to display images. The liquid crystal molecules have orientation characteristics of arrangement resulting from their thin and long shape. Thus, an arrangement direction of the liquid crystal molecules can be controlled by applying an electrical field to them. Accordingly, when the electric field is applied to them, polarization properties of light is changed according to the arrangement of the liquid crystal molecules such that the LCD devices display images.
Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
The LCD device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. A common electrode and a pixel electrode are respectively formed on the first and second substrates. The first and second substrates may be referred to as a color substrate and an array substrate, respectively. The liquid crystal layer is driven by a vertical electric field induced between the common and pixel electrodes. The LCD device has excellent transmittance and aperture ratio.
However, the LCD device using a vertical electric field has a narrow viewing angle. To overcome this problem, an IPS mode LCD device having a wide viewing angle is suggested.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the IPS mode LCD device 1 includes an array substrate “AS,” a color filter substrate “CS” and a liquid crystal layer “LC.” The array substrate “As” and the color filter substrate “CS” face each other, and the liquid crystal layer “LC” is interposed therebetween. The array substrate “AS” includes a first substrate 10 including a pixel regions “P,” a thin film transistor “T,” a plurality of common electrodes 18 and a plurality of pixel electrodes 32. The thin film transistor “T,” the plurality of common electrodes 18 and the plurality of pixel electrodes 32 are formed in the pixel region “P.” The thin film transistor “T” is disposed in the pixel region “P” and includes a gate electrode 12, a semiconductor layer 22, a source electrode 24 and a drain electrode 26. The source and drain electrodes 24 and 26 are spaced apart from each other.
Although not shown, a gate line connected to the gate electrode 12 is formed along a first direction on the first substrate 10, and a data line connected to the source electrode 24 along a second direction on the first substrate 10. The gate line crosses the data line to define the pixel region “P.” In addition, although not shown, a common line, which is connected to the plurality of common electrodes 18 and parallel to the gate line, is formed along the first direction on the first substrate 10. The common electrode 18 is formed with the same material at the same layer as the gate electrode 12, and the pixel electrode 32 includes a transparent conductive material.
The color filter substrate “CS” includes a second substrate 40, a black matrix 42 and a color filter layer 44. The black matrix 42 shields portions except for the plurality of pixel regions “P.” The color filter layer 44 is formed on the black matrix 42 and corresponds to the plurality of pixel regions “P.” Particularly, the color filter layer 44 including a red sub-color filter 44a, a green sub-color filter 44b and a blue sub-color filter (not shown).
The liquid crystal layer “LC” is driven by a horizontal electric field (not shown) induced between each common electrode 18 and each pixel electrode 32.
Further, a gate insulating layer 20 and a passivation layer 31 are disposed between the common electrode 18 and the pixel electrode 32. At this time, at a step difference due to the gate insulating layer 20 and the passivation layer 31 interposed between the common electrode 18 and the pixel electrode 32, liquid crystal molecules of the liquid crystal layer “LC” may be abnormally arranged because of electric field distortion at the step difference. Therefore, the electric field distortion causes disclination. To solve the problem, a structure that the common electrode is formed with the same material at the same layer as the pixel electrode without any step difference therebetween is suggested.
FIG. 2A is a schematic plan view of an array substrate for an IPS mode LCD device with respect to one pixel region according to the related art, and FIG. 2B is a schematic cross-sectional view taken along a line “IIb-IIb” of FIG. 2A according to the related art.
In FIGS. 2A and 2B, a gate line 52 and a data line 68 crossing the gate line 52 are formed in a substrate 50 to define a pixel region “P.” A thin film transistor “T” is formed at crossing of the gate and data lines 52 and 68 and includes a gate electrode 54, an active layer 60, a source electrode 64 and a drain electrode 66. A common electrode 74 and a pixel electrode 72 are disposed in the pixel region “P.” Specifically, the common electrode 74 includes a first common electrode pattern 74a and a second common electrode pattern 74b diverged from the first common electrode pattern 74a, and the pixel electrode 72 includes a first pixel electrode pattern 72a and a second pixel electrode pattern 72b diverged from the first pixel electrode pattern 72a. In particular, the second common electrode pattern 74b and the second pixel electrode pattern 72b are alternately arranged with each other in the pixel region “P” to generate a horizontal electric field (not shown). The common electrode 74 is connected to a common line 73 parallel with the gate line 52, and the pixel electrode 72 is connected to the drain electrode 66. An auxiliary common electrode 56 extends from the common line 73 and includes first to fourth auxiliary common electrode patterns 56a, 56b, 56c and 56d having a tetragonal frame shape.
Here, the first auxiliary common electrode pattern 56a as a first capacitor electrode, the first pixel electrode pattern 72a as a second capacitor electrode with a gate insulating layer 57 and a passivation layer 69 therebetween as insulators constitute a storage capacitor “Cst.”
According to the related art, to obtain a large capacity by increasing the size of the storage capacitor “Cst,” the first auxiliary common electrode 56a and the first pixel electrode pattern 72a are manufactured with a relative large size. Therefore, the aperture region is reduced, so it is difficult to obtain a high aperture ratio, a high brightness and a high resolution.
In addition, because the common electrode 74 and the pixel electrode 72 are formed with the same material at the same layer as each other, the common electrode 74 and the pixel electrode 72 should have a predetermined distance with each other to prevent shorting defect between the common electrode 74 and the pixel electrode 72. In particular, the shorting defect may be generated at gap spaces between an end portion of the second common electrode pattern 74b and the first pixel electrode pattern 72a and between an end portion of the second pixel electrode pattern 72b and the first common electrode pattern 74a. 
In particular, horizontal electric fields between the first common electrode pattern 74a and the second pixel electrode pattern 72b and between the second common electrode pattern 74b and the first pixel electrode pattern 72a are easily distorted, so there is a problem that the horizontal electric fields badly affects movement of the liquid crystal molecules of the liquid crystal layer “LC.”
FIG. 3 is an expanded plan view regarding an area “III” of FIG. 2A according to the related art.
In FIG. 3, two second common electrode patterns 74b are diverged from the first common electrode pattern 74a along the second direction. The second pixel electrode pattern 72b is disposed between the two second common electrode patterns 74b to be in parallel with each other. Further, an end portion of the second pixel electrode pattern 72b is spaced apart from the first common electrode pattern 74a to prevent a shorting defect as above.
Therefore, although a first horizontal electric field “F1” between the second common electrode pattern 74a and the second pixel electrode pattern 72b in a main portion of the pixel region “P” is normally generated, a second horizontal electric field “F2” between an end portion of the second pixel electrode pattern 72b and the first common electrode pattern 74a is electrically distorted.
As a result, because first and second arrangement features of the liquid crystal molecules in accordance with the first and second horizontal electric fields “F1” and “F2” are different from each other, optical properties in accordance with the first and second horizontal electric fields “F1” and “F2” are also different from each other. Therefore, for example, brightness property at a peripheral area “LK” is different from that of the main area of the pixel region “P,” so light leakage occur in the peripheral area “LK.”
As a result, the peripheral area “LK” should be shielded to prevent reducing an image quality, so the aperture region is reduced. Consequently, the aperture ratio, the brightness, and the resolution are reduced.
Further, to obtain an enough capacity, the storage capacitor is manufactured with a relative large size, so it is difficult to obtain a high aperture ratio.